VERILOG-BASED IMPLEMENTATION OF THE AMBA AXI PROTOCOL

Abstract

The key characteristics of the advanced extensible interface (AXI) are the primary emphasis of
this study. When checking the AXE I memory transactions, be sure to check the write address, write data,
write response, read address, and read data on each of the five channels. The verification process in this
work is carried out using a technique based on verification intellectual property cores (VIP). Using the
quantitative values of Busy Count, Valid Count, and its Bus Utilisation, the VIP design validates read and
write transactions from the same and different memory locations in the test environment that is modelled
using system verilog. One of the basic aspects validated in this work is the system connection throughout
write and read cycles.